In a data communication and the like, in view of the fact that a decoder for performing a decoding processing for received data by means of performing an error correction processing involving a soft decision processing is more excellent in accuracy of an error correction as compared with a decoder for performing a decoding processing for received data by means of performing an error correction processing involving a hard decision processing, it is general to adopt the decoder involving the soft decision processing. In the hard decision processing, it is decided that the received data is associated with a logic ‘0’ or a logic ‘1’. In the soft decision processing, a voltage between an ‘L’ level voltage indicative of a logic ‘0’ and an ‘H’ level voltage indicative of a logic ‘1’ is divided into several levels to decide which level the actually received data is associated with.
Further, hitherto, in a mobile communication and the like, in order to effectively transmit a plurality of data through a channel physically determined, an encoder at the transmission side transmits a data sequence obtained by means of deletion of a part of data or a supplement of the same data in accordance with a predetermined rule. A decoder at the receiving side decodes data in accordance with the predetermined rule in such a manner that when the decoder receives a data sequence wherein a part of data is deleted, the deleted data is supplemented, and when the decoder receives a data sequence wherein the same data is supplemented, the supplemented data is deleted, and further an error correction processing is performed.
A communication path of the actual communication system is easy to be affected by noises due to variations (fading) in the field strength of a radio wave. For this reason, it may happen that received data offers a middle level voltage between an ‘L’ level voltage representative of logic ‘0’ and an ‘H’ level voltage representative of logic ‘1’. In the event that received data having such an indefinite level, it may happens that a decoder involving the soft decision processing is degraded in correction accuracy and is elongated in time until it converges on a desired error correction accuracy.
Further, due to the above-mentioned fading occurence, an electric power of received data is in part weakened or a phase of a wave representative of the received data is changed, and as a result, a reliability of a part of data of the received data is degraded. Under such a state, in the event that a data sequence wherein the same data is supplemented is received, it may happen that only the data of lower reliability is selected in connection with a procedure of deletion of the same data in accordance with a predetermined rule. In such a case, although the data of higher reliability is received, the data of higher reliability is annulled, so that error correction ability may be lowered. Thus, it may happen that it is difficult to decode the transmitted data with great accuracy.
Japanese Patent Laid Open Gazette Hei. 10-303759 proposes a technique of correcting a bit sequence after an error correction processing.
FIG. 5 is a block diagram of a decoder proposed in Japanese Patent Laid Open Gazette Hei. 10-303759.
A decoder 100 shown in FIG. 5 comprises demodulating means 110, Viterbi decoding means 120, CRC means 130 and bit inverting means 140.
The demodulating means 110 receives, in unit of a predetermined data sequence, received data Y modulated in accordance with predetermined modulation techniques. The demodulating means 110 demodulates the entered received data Y, and generates soft decision data in accordance with amplitude and phase of a wave representative of the received data Y and outputs the same to the Viterbi decoding means 120.
The Viterbi decoding means 120 performs an error correction processing in accordance with a predetermined algorithm determined between the receiving side and the transmission side beforehand, based on the soft decision data output from the demodulating means 110, and decodes the processed data to a bit sequence of data, and further adds reliability information to the bit sequence of data and then outputs the same to the CRC means 130.
The CRC means 130 performs a CRC test for the entered bit sequence of data. As a result of the CRC test, in the event that no error is decided, data of the bit sequence is output in form of decoding data D. On the other hand, in the event that an error is decided, data of the bit sequence is output toward the bit inverting means 140.
The bit inverting means 140 performs a bit inversion for data of the entered bit sequence in order that the sum of reliability information of the inverted bits becomes smaller to generate data of a new bit sequence and feedback the same to the CRC means 130. In this manner, the processing by the CRC means 130 and the bit inverting means 140 is repeated until no error is decided, so that accuracy in error correction is enhanced and a time up to converging on a desired error correction accuracy is reduced.
However, the repeated processing by the CRC means 130 and the bit inverting means 140 does not consider characteristics of the demodulation algorithm used, since it is based on data of the bit sequence subjected to the hard decision processing from the Viterbi decoding means 120. Accordingly, it is insufficient in accuracy of the error correction. Further, there is a possibility that the number of times of bit inversion is increased. Accordingly, there is a possibility that a total time of the decoding processing is lengthened.